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Ordering number : ENN*6614A
CMOS IC
LC898023KW, 898023KL
40x Playback/16x Write CD-R/RW Encoder/Decoder IC with Built-in SCSI Interface
Preliminary Functions
* * * * * * * * * * CD-ROM decoder/encoder functions CD decoder/encoder functions Pit and wobble CLV servo CAV audio functions SCSI interface (includes the register block) Subcode encoder/decoder functions ATIP demodulator/ATIP decoder Supports BURN-Proof recording Write strategy function (CD-R/RW) CD-DSP function with built-in digital servo * * * * CAV audio functions Write strategy function supports 16x recording. Built-in SCSI interface (supports Ultra SCSI) Supports 40x decoding and 16x encoding. Clock frequencies: CD-ROM block: 33.8688 MHz, SCSI block: 20 MHz Ultra SCSI data transfer rate: 20 Mbyte/s (Maximum synchronous transfer rate), Fast SCSI: 10 Mbyte/s (Maximum synchronous transfer rate), 5 Mbyte/s (Maximum asynchronous transfer rate) Uses 16-bit data bus 45 ns EDO DRAM. From 1 to 64 Mbits of buffer RAM can be used. (16-bit data bus EDO DRAM) The user can freely set up the CD main channel, C2 flag, and subcode areas in buffer RAM. Batch transfer function (Function for transferring the CD main channel, C2 flag, subcode, and other data in a single operation) Multi-transfer function (Function for automatically transferring multiple blocks to the host in a single operation)
*
* * *
Features
* ECC and EDC correction/addition (decoding/encoding) for CD-ROM data. * ECC error correction/addition (decoding/encoding) for subcode data * Servo control implemented in a digital servo system (decoding/encoding) * Wobble CLV servo control using ATIP data (encoding) * ATIP decoding function and CRC check function (decoding/encoding) * CIRC code generation and addition and EFM modulation (encoding)
*
"BURN-Proof" stands for Proof against Buffer Under RuN error, not for proof against burning. "BURN-Proof" is a trademark of SANYO Electric Co.,Ltd. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
20802TN (OT)/82500RM (OT) No. 6614-1/13
LC898023KW, 898023KL
Package Dimensions
unit: mm 3261-SQFP208J (28 x 28)
[LC898023KW]
31.2 0.8 28.0
unit: mm 3264-LQFP208
[LC898023KL]
30.0 28.0 25.5
156 157
105 104 157 156
105 104
(1.4)
0.10
28.0
31.2
28.0
208 1
(0.5) (1.25) 0.2
53 208 52
(3.2) 0.15
53 1
0.5 0.22
52
25.5
30.0
0.09
3.56max
0.1
1.6max
0.5
(0.5)
SANYO: SQFP208J (28 x 28)
SANYO: LQFP208
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Supply voltage Symbol VDD5 max VDD3 max VI5, VO5 VI3, VO3 Pd max Topr Tstg 10 seconds Ta 25C Ta 25C Ta 25C Ta 25C Ta 70C Conditions Ratings -0.3 to +6.0 -0.3 to +4.6 -0.3 to VDD5 + 0.3 -0.3 to VDD3 + 0.3 900 -30 to +70 -55 to +125 260 Unit V V V V mW C C C
I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering conditions (pins only)
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter [I/O cells, 5.0 V power supply] Supply voltage Input voltage range [Internal cells, 3.3 V power supply] Supply voltage Input voltage range VDD3 VIN 3.0 0 3.3 3.6 VDD3 V V VDD5 VIN 4.5 0 5.0 5.5 VDD5 V V Symbol Conditions Ratings min typ max Unit
No. 6614-2/13
LC898023KW, 898023KL Electrical Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Analog input voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Analog output voltage Input leakage current Output leakage current Pull-up resistance Pull-up resistance Symbol VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VANI VOH VOL VOH VOL VOH VOL VOL VOL VOL VOH VOL VOH VOL VANO IIL IOZ RUP RUP Conditions Ratings min 2.2 0.8 2.2 0.8 2.5 0.6 2.0 0.8 0.8 VDD 0.2 VDD 0.7 VDD 0.3 VDD 1/4 VDD VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 0.4 0.4 0.4 VDD - 2.1 0.4 2.4 0.4 1/4 VDD -10 -10 40 50 80 100 3/4 VDD +10 +10 160 200 3/4 VDD typ max Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V A A k k
TTL level inputs: (2), (14)
TTL level inputs with built-in pull-up resistors: (13)
TTL level Schmitt trigger inputs: (1)
(15)
CMOS level Schmitt trigger inputs: (3)
CMOS level inputs with built-in pull-up resistors: (4) (5) IOH = -12 mA: (8) IOL = 12 mA: (8) IOH = -8 mA: (7) IOL = 8 mA: (7) IOH = -2 mA: (6), (13), (14) IOL = 2 mA: (6), (13), (14) IOL = 48 mA: (15) IOL = 8 mA: (12) IOL = 1 mA: (9) IOH = -4 mA: (11) IOL = 4 mA: (11) IOH = -6 mA: (16), (17) IOL = 6 mA: (16), (17) (10) VI = VSS, VDD: (1), (2), (14), (15) In the high-impedance output state: (9), (11), (12) (12), (13) (4)
The applicable pin groups are listed on the following page.
No. 6614-3/13
LC898023KW, 898023KL Applicable Pins [INPUT] (1) * * * * * * WOBBLE, CS, RD, WR, DEF, HFL, TES, RESET (2) * * * * * * SUA0 to SUA7, TEST0 to TEST4 (3) * * * * * * WRITE (4) * * * * * * FG (5) * * * * * AD0, AD1, RREC, FE, TE, VREF, FR, OPP, JITIN, PCKISTF, PCKISTP, EFMIN, EFMIN2, SLCIST1, SLCIST2 [OUTPUT] (6) * * * * * * LDON (7) * * * * * EFMG, SHOCK, LOCK, EFMO, SSP2/1, RAPC, WAPC, H11TO, LDH, ATEST3, ATEST1, WDAT, NWDAT (8) * * * * * * PCK2, SUBSYNC (9) * * * * * * PDS1 to PDS3 (10) * * * * * DA0 to DA2, TDO, FDO, SLDO, SPDO, JITC, LOUT, ROUT, PDO, RPO, SLDO, SLCO1 to SLCO3 (11) * * * * * DSLB (12) * * * * * INT0, INT1, SWAIT (16) * * * * * RA0 to RA9, CAS0 to CAS1, RAS0 to RAS2, LWE, UWE, OE [INOUT] (13) * * * * * D0 to D7 (17) * * * * * ID0 to ID15 (14) * * * * * ATIPSYNC, BICLK, BIDATA, ACRCNG (15) * * * * * ACK, ATN, BSY, C/D, DB0 to DB7, DBP, I/O, MSG, REQ, RST, SEL Note: The XTAL0, XTAL1, XTALCK0, and XTALCK1 are not included in the DC characteristics. SCSI Pin Input Characteristics
Parameter Symbol Vt + t1 Vt - t1 Vtt1 VDD = 4.50 to 5.50 V VDD = 4.50 to 5.50 V VDD = 5.0 V 0.80 0.41 Conditions Ratings min typ 1.60 1.10 0.5 max 2.00 Unit V V
Input threshold voltage Hysteresis width
Active Negation Output Characteristics
Parameter Output high voltage Output low voltage Symbol VOH VOL Conditions Ratings min 2.5 0.4 typ max Unit V V
Note: The active negation output characteristics only applies to DB0 to DB7, REQ, and DBPB
Rise Time Test Circuit
SCSI Driver TP 475%
15pF5%
+ -- 2.5V
A13480
No. 6614-4/13
LC898023KW, 898023KL Block Diagram LC898023K
Data bus[0:7] Write Strategy & Link-position ATIP/CLV servo ATIPSYNC Sub-code I/F de-interleve/interleve Digital Servo & CIRC EnDec Address generator Sub-code ECC Address generator *10 RAM Data bus[0:15] Address bus[0:21]
*12
*1 *2
CAV-Audio
DAC
*13
CD-DSP I/F & SYNC Detector
De-scramble & Buffering Address generator
ECC & EDC Address generator HOST *3 SCSI I/F Block Each Block Register R0-R87 decoder Address generator
Each Block Bus control signal External Bus Arbiter & DRAM controller *8 *9 Buffer
INT0, INT1 *6 Micro controller *7 SWAIT XTALCK0 XTAL0
DRAM Data output input I/F
PLL & Clock generator Each Block
Microcontroller RAM access Address generator TEST0-4
XTALCK1 XTAL1 SCSI Block
A13483
*1 *2 *3 *6 *7 *8 *9 *10 *12 *13
DSLB (pin96) to FR (pin123), CSS (pin126) to SPDO (pin142), SHOCK (pin147) to PCK2 (pin155) SUBSYNC DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D, ACK, ATN RD, WR, SUA0 to SUA7, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE, BIDATA, BICLK, ATIPSYNC WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, TEST2/1, WDAT, NWDAT, EFMG LOUT, ROUT
No. 6614-5/13
LC898023KW, 898023KL Pin Functions
Pin type I O Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin name VSS RA4 RA5 RA6 RA7 RA8 RA9 VDD VSS IO0 IO1 IO2 IO3 IO4 IO5 VDD VSS IO6 IO7 IO8 IO9 IO10 VSS VDD IO11 IO12 IO13 IO14 IO15 ATIPSYNC BIDATA BICLK WOBBLE VDD VSS ACRCNG WRITE SSP2 SSP1 RAPC WAPC H11T0 LDH VDD VSS ATEST3 ATEST1 WDAT NWDAT VDD VSS Type P O O O O O O P P B B B B B B P P B B B B B P P B B B B B I B B I P P O I O O O O O O P P O O O O P P Digital system power supply (5 V) Digital system ground (VSS) ATIP CRC error signal Write strategy signal control input Servo sampling pulse output Servo sampling pulse output Laser control sampling pulse output Laser control sampling pulse output Running OPC sampling pulse Recording laser diode control signal output Digital system power supply (3.3 V) Digital system ground (VSS) Analog block test output Analog block test output Recording laser diode control signal output Recording laser diode control signal output (WDAT inverted) Analog system power supply (3.3 V) Analog system ground (VSS) ATIP demodulator I/O signals ATIP SYNC detection signal CD-ROM encoder/decoder buffer RAM data lines Digital system ground (VSS) Digital system power supply (3.3 V) CD-ROM encoder/decoder buffer RAM data lines These pins have built-in pull-up resistors. Digital system power supply (3.3 V) Digital system ground (VSS) CD-ROM encoder/decoder buffer RAM data lines These pins have built-in pull-up resistors. Digital system power supply (5 V) Digital system ground (VSS) CD-ROM encoder/decoder DRAM address lines Digital system ground (VSS) Input Output Pin function B P Bidirectional pin Power supply NC A Not connected Analog pin
Continued on next page.
No. 6614-6/13
LC898023KW, 898023KL
Continued from preceding page.
Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Pin name VDD VSS R1 VCNT1 MDC1 PD1 SWAIT INT0 INT1 D0 D1 D2 D3 D4 D5 D6 VDD VSS D7 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 SUA7 CS RD WR TEST0 VCNT R PD VDD VSS TEST1 RESET XTALCK0 XTAL0 ROUT VSS VDD LOUT DSLB SLCIST1 SLCIST2 VSS VDD SLCO0 SLCO1 SLCO2 VDD VSS Type P P I I I O O O O B B B B B B B P P B I I I I I I I I I I I I I I O P P I I I O O P P O O I I P P O O O P P Digital system power supply (5 V) Digital system ground (VSS) EFM slice level output Chip select signal input from the microcontroller Data read signal from the microcontroller Data write signal from the microcontroller Test pin. This pin must be tied to VSS. VCO control voltage VCO bias resistor connection Charge pump output Analog system power supply (3.3 V) Analog system ground (VSS) Test pin. This pin must be tied to VSS. Reset input Crystal oscillator circuit input (33.8688 MHz) Crystal oscillator circuit output D/A converter output Analog system ground (VSS) Analog system power supply (5 V) D/A converter output SLC PWM output EFM slice level setting input Analog system ground (VSS) Analog system power supply (3.3 V) Command register selection address Digital system power supply (5 V) Digital system ground (VSS) Microcontroller data signal line Microcontroller data signal lines These pins have built-in pull-up resistors. Wait signal to the microcontroller Interrupt request signal outputs to the microcontroller These are open-drain outputs with built-in pull-up resistors. Write strategy analog signals Digital system power supply (5 V) Digital system ground (VSS) Pin function
Continued on next page.
No. 6614-7/13
LC898023KW, 898023KL
Continued from preceding page.
Pin No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin name SLCO3 EFMIN EFMIN2 TEST4 JITC RPO OPP PCKISTF PCKISTP VSS VDD PDO PDS1 PDS2 VDD VSS PDS3 FR TEST2 TEST3 CSS AD0 RREC FE TE VREF AD1 VSS DA0 DA1 DA2 TDO VDD VSS FDO SLDO SPDO VSS VDD SUBSYNC EFMG SHOCK LOCK DEF HFL TES EFMO LDON FG PCK2 VDD VSS XTALCK1 XTAL1 DB0 Type O I I I O O I I I P P O O O P P O I I I I I I I I I I P O O O O P P O O O P P O O O O I I I O O I O P P I O B EFM slice level output EFM input Test pin. This pin must be tied to VSS. Jitter output P/N balance adjustment Frequency comparator charge pump Phase comparator charge pump Analog system ground (VSS) Analog system power supply (3.3 V) Charge pump filter Charge pump selection Digital system power supply (3.3 V) Digital system ground (VSS) Charge pump selection VCO frequency setting Test pin. This pin must be tied to VSS. DRAM voltage (5 V/3.3 V) selection pin Center servo input pin AD input Optical signal discrimination input FE input TE input VREF input AD input Analog system ground (VSS) DA output DA output DA output Tracking output Analog system power supply (5 V) Analog system ground (VSS) Focus output Sled output Spindle output Digital system ground (VSS) Digital system power supply (3.3 V) Subcode SYNC signal EFM gate signal Shock detection signal output PLL lock state output Defect detection signal input Mirror detection signal input TES comparator input Post-binarization EFM signal output Laser control FG input PCK output Digital system power supply (5 V) Digital system ground (VSS) SCSI interface crystal oscillator circuit input (20 MHz) SCSI interface crystal oscillator circuit output SCSI connection Pin function
Continued on next page. No. 6614-8/13
LC898023KW, 898023KL
Continued from preceding page.
Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 RAS0 RAS1 RAS2 LWE VDD VSS UWE CAS0 CAS1 OE RA0 RA1 RA2 RA3 VDD Pin name VSS DB1 DB2 VDD DB3 DB4 VSS DB5 DB6 DB7 VSS VDD VSS DBP ATN BSY VSS ACK RST VDD MSG SEL VSS C/D VSS VDD REQ I/O VSS VDD VSS Type P B B P B B P B B B P P P B B B P B B P B B P B P P B B P P P NC NC O O O O P P O O O O O O O O P Digital system power supply (3.3 V) CD-ROM encoder/decoder DRAM address lines DRAM lower write enable Digital system power supply (3.3 V) Digital system ground (VSS) DRAM upper write enable DRAM CAS signal output DRAM output enable DRAM RAS signal outputs Digital system ground (VSS) SCSI connection Digital system power supply (5 V) SCSI connection Digital system ground (VSS) SCSI connection Digital system ground (VSS) Digital system power supply (5 V) SCSI connections Digital system ground (VSS) Digital system power supply (3.3 V) Digital system ground (VSS) Unused Unused SCSI connection Digital system ground (VSS) Digital system power supply (5 V) Digital system ground (VSS) SCSI connection Digital system ground (VSS) SCSI connection Digital system power supply (5 V) SCSI connection Digital system ground (VSS) Pin function
No. 6614-9/13
LC898023KW, 898023KL Pin Functions BSY, ACK, MSG, SEL, REQ, ATN, RST, I/O, C/D (input/output) SCIS bus control. DB0 to DB7, DBP (input/output) SCSI data bus. CS (input) Chip select signal from the microcontroller. The microcontroller interface is active when this pin is low. RD, WR (input) Connect the microcontroller read and write lines to these inputs. SWAIT (input) Wait signal output to the microcontroller. When accessing buffer RAM, the microcontroller must wait if this pin is low. SUA0 to SUA7 (input) Internal register address lines D0 to D7 (input) Microcontroller data bus. These pins have built-in pull-up resistors. INT0, INT1 (output) Interrupt request signals output to the microcontroller. INT1 can be set to output the ATAPI interrupt by setting INT1EN (Conf-R11 bit 7) These are open drain outputs with built-in 80 k (at room temperature, 5 V) pull-up resistors. I/O0 to I/O15 (input/output) Buffer RAM data bus. These pins have built-in pull-up resistors. RA0 to RA9 (output) Buffer RAM address lines. RAS0, RAS1, RAS2 (output) Buffer DRAM RAS outputs. Normally, RAS0 is used. However, if two 16-Mbit DRAMs are used, connect the RAS0 and RAS1 lines to the RAS pins on the DRAMs. If four 16-Mbit DRAMs are used, connect the RAS0, RAS1, RAS2, and LWE lines to the RAS pins on the DRAMs. CAS0, CAS1 (output) Buffer DRAM CAS outputs. Normally, CAS0 is used. However, if two 16-Mbit DRAMs are used, connect the CAS0 output to the CAS pins on the DRAMs. If 2-CAS type DRAMs are used, connect CAS0 to UCAS and CAS1 to LCAS. OE (output) Buffer RAM read output. UWE, LWE (output) Buffer RAM write outputs. Connect these to the corresponding pins. If 2-CAS type DRAMs are used, UWE must be connected. (Leave LWE open.) 1. Analog Interface Pins CCS (input) Midpoint servo input pin. RREC (input) Optical discrimination input. FE (input) Focus error signal input. TE (input) Tracking error signal input. VREF (input) Input for the servo system reference voltage.
No. 6614-10/13
LC898023KW, 898023KL AD0, AD1, AD2 (input) A/D converter auxiliary inputs. DA0, DA1, DA2 (input) D/A converter auxiliary inputs. TES (input) TES comparator input. TDO (output) Tracking control signal output. FDO (output) Focus control signal output. SLDO (output) Sled control signal output. SPDO (output) Spindle control signal output. 2. EFM Input Block Pins EFMIN (input) EFM signal input. The high-frequency components of the RF signal acquired from the RF amplifier are cut with a capacitor, and this pin inputs that signal biased by the value of the SLCO0 to SLCO3 outputs passed through a low-pass filter. EFMIN2 (input) Used to change the time constant of the low-pass filter. SLCIST1, SLCIST2 (input) Slice level controller charge pump bias resistor connection. SLCO0, SLCO1, SLCO2, SLCO3 (output) Slice level controller charge pump outputs. These levels bias the RF signal input to the EFMIN pin after being passed through a low-pass filter. DSLB (output) Slice level control PWM output. EFMO (output) Post-binarization EFM signal output. (For monitoring) 3. EFM Clock Generation Block Pins FR (input) EFM reproduction PLL VCO bias resistor connection. PDO, PDS1, PDS2, PDS3 (output) EFM reproduction PLL lag-lead filter connection. PCKISTF (input) EFM reproduction PLL frequency comparator charge pump bias resistor connection. PCKISTP (input) EFM reproduction PLL phase comparator charge pump bias resistor connection. RPO (output) P/N balance adjustment. OPP (input) P/N balance adjustment. PCK2 (output) EFM reproduction bit clock output. 4. Jitter Discrimination Pins JITC (output) Jitter output.
No. 6614-11/13
LC898023KW, 898023KL 5. Spindle Speed Detection Pins FG (input) Input for the speed monitor signal from the spindle driver. 6. Audio Interface Pins LOUT, ROUT (output) Left and right channel audio signal outputs. 7. RF Amplifier Interface Pins LDON (output) RF amplifier interface. 8. Write Strategy Pins WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, 1, WDAT, NWDAT (I/O) Write strategy signal connections. 9. ATIP Decoder Related Pins ATIPSYNC (output) ATIP synchronization detection signal. (For monitoring) BIDATA, BICLK (I/O) Input mode: Input of the biphase data and biphase clock when an external ATIP demodulator is used. Output mode: Output of the biphase data and biphase clock when the internal ATIP demodulator is used. (For monitoring) WOBBLE (input) Wobble signal is input when the internal ATIP demodulator is used. ACRCNG (output) Outputs the result of the ATIP decoder CRC check. (For monitoring) RESET (input) The LC898023K reset input. A low level input resets the LC898023K. This pin must be held low for at least 1 s when power is first applied. TEST4 to TEST0 (input) Test inputs. These pins must be connected to ground. XTALCK0 (input), XTAL0 (output) Drive these pins at 33.8688 MHz. This signal is used, without modification, as main clock for the CD-ROM encoder and decoder blocks, including the DRAM interface. XTALCK1 (input), XTAL1 (output) Main clock for the SCSI block. The LC898023K is designed so that it can operate even when the ECC and SCSI blocks are not synchronized. Providing a 20 MHz input to the XTALCK0 and XTALCK1 pins assures that correct, synchronized transfer at 10 Mbyte/s (20 Mbyte/s for Ultra SCSI) can be achieved. The maximum frequency that can be used is 20 MHz. Since both edges of the clock signal are used by Ultra SCSI, the duty ratio must be correct. Add feedback resistors on the XTALCK1 and XTAL1 pins and take other measures as required. R, VCNT, PDO, R1, VCNT1, PD1, MDC1 (I/O) Clock reproduction PLL circuit pins. SUBSYNC (output) Subcode SYNC output signal from the CIRC encoder during recording. (For monitoring) EFMG (output) Outputs a high level during recording. SHOCK (output) Outputs a high level when a mechanical shock is detected.
No. 6614-12/13
LC898023KW, 898023KL LOCK (output) Outputs a high level when the PLL circuit is locked. DEF (input) Inputs the defect detection signal. HFL (input) Inputs the mirror detection signal.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 2002. Specifications and information herein are subject to change without notice. PS No. 6614-13/13

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